The present disclosure relates to integrated circuit (IC) fabrication, and more specifically, to an IC including a long channel fin-type field effect transistor (FinFET) having source/drain regions below a semiconductor fin in a semiconductor substrate. Methods of forming the IC are compatible with simultaneously forming a vertical FinFET.
In integrated circuits, fin-type field effect transistors are used widely to create various devices. With conventional FinFETs, source/drain regions are formed in a semiconductor fin, e.g., by implanting dopants, and a gate is created over or against the fin. The area of the fin within the gate creates a channel for the transistor structure. When the gate is active, current travels laterally through the fin between the source/drain regions therein. One can adjust channel length by adjusting the distance between the source/drain regions in the fin. Controlling channel length controls a number of performance factors for a transistor structure such as current leakage, threshold voltage, responsiveness, reliability, etc.
Vertical FinFETs include a semiconductor fin with one source/drain region formed below the fin, and another source/drain region formed atop the fin, and a gate formed about the semiconductor fin. A channel is formed within the gate in the fin. When the gate is active, current travels vertically within the fin between the source/drain regions. Vertical FinFETs are the desired structure for the 5 nanometer technology node and beyond because they allow scaling of the source/drain regions and channel within the same areal footprint, i.e., because they are vertically arranged.
One challenge with vertical FinFETs is creating a long channel device with other vertical FinFETs. In particular, forming a long channel device requires increasing fin height, which raises the overall height of the transistor structure in such a way that it may not be compatible with other vertical FinFETs within the integrated circuit. One approach to address this challenge, shown in FIG. 1, includes creating a laterally long channel bulk FET 10 with vertical FinFETs 12. Vertical FinFETs 12 include a lower source/drain region 14 in semiconductor substrate 16, a semiconductor fin(s) 18 extending from semiconductor substrate 16 and an upper source/drain region 20 over semiconductor fin(s) 18, e.g., epitaxially grown. A gate 22 including an upper spacer 24 and a lower spacer 26 surrounds semiconductor fin(s) 18. On the far right side, a long channel FET 10 is shown. Here, a lower spacer (26 on left) is removed, and a lower source/drain region 32 is moved laterally within substrate 16 from under a gate 34. A conventional gate dielectric 35 may be used between gate 34 and other structure. In any event, long, cornered channel 36 (path with arrows) is formed from upper source/drain region 38 through semiconductor fin 40, through semiconductor substrate 16 to lower source/drain region 32. This arrangement suffers from a number of issues. First, etching to remove lower spacer (26 on left) (see enlarged area) creates a surface roughness and curved surface 42 in the etch direction, which makes control of the length of cornered channel 36 very difficult. The long cornered channel 36 also creates reliability concerns for input/output devices due to the corner, and a double channel (fin 38 and substrate 16) in series results in poor device performance. Further, this process requires an additional masking step to protect other structure during removal of the lower spacer (26 on left) for the long channel FET 10.
Another approach is shown in FIG. 2. In this approach, a long channel device 50 uses a pair of fins 52, 54 to contact a long channel bulk FET 60 (arrows). Vertical FinFETs 12 are identical to those described relative to FIG. 1. Here, source/drain regions 56, 58 are formed on top of each fin 52, 54 and a lower spacer (26 on left) is removed therebetween, creating a channel 60 that is U-shaped. Gate 62 surrounds both fins 52, 54. A conventional gate dielectric 55 may be used between gate 62 and bulk channel. The formation process for this type long channel device 50 suffers from the same shortcomings as that of the arrangement of FIG. 1.
It is very difficult to create a long channel device, or long channel input/output device, with vertical FinFETs.